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edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis pin configuration (top view) time (min.ns) cycle dissipa- (typ.mw) power tion dq 1 outline 26p3z-e (300mil tsop) dq 2 a 0 a 1 a 2 w ras a 3 v cc a 9 1 2 3 4 5 13 12 11 10 9 v ss dq 4 dq 3 cas oe a 4 a 7 a 6 a 5 16 15 26 25 24 23 17 18 22 14 a 8 standard 26 pin soj, 26 pin tsop(ii) single 3.3v?.3v supply low stand-by power dissipation cmos lnput level .................................................1.8mw(max)* cmos lnput level ................................................180?(max) low operating power dissipation m5m4v4405cxx-6, -6s .....................................288.0mw (max) m5m4v4405cxx-7, -7s ....................................252.0mw (max) self refresh capabiility * self refresh current ..............................................100?(max) extended refresh capability * extended refresh current ....................................100?(max) hyper-page mode (1024-bit random access), read-modify- write, ras-only refresh cas before ras refresh, hidden refresh, cbr self refresh(-6s,-7s) capabilities. early-write mode and oe and w to control output buffer impedance 1024 refresh cycles every 16.4ms (a 0 ~a 9 ) 1024refresh cycle every128ms (a 0 ~a 9 ) * *: applicable to self refresh version (m5m4v4405cxx-6s,-7s: option) only this is a family of 1048576-word by 4-bit dynamic rams, fabricated with the high performance cmos process,and is ideal for large-capacity memory systems where high speed, low power dissipation , and low costs are essential. the use of quadruple-layer polysilicon process combined with silicide technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. multiplexed address inputs permit both a reduction in pins and an increase in system densities. self or extended refresh current is low enough for battery back-up application. 1 description features type name ras cas address m5m4v4405cxx-7, -7s 70 20 35 130 231 20 oe m5m4v4405cxx-6, -6s 60 15 30 110 264 15 pin description pin name a 0 ~a 9 dq 1 ~dq 4 ras w v cc v ss cas function oe edo (hyper page mode) 4194304-bit (1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis dq 1 outline 26p0j (300mil soj) dq 2 a 0 a 1 a 2 w ras a 3 v cc a 9 1 2 3 4 5 13 12 11 10 9 v ss dq 4 dq 3 cas oe a 4 a 7 a 6 a 5 16 15 26 25 24 23 17 18 22 14 a 8 xx=j, tp application lap top personal computer,solid state disc, microcomputer memory, refresh memory for crt access time (max.ns) access time (max.ns) access time (max.ns) access time (max.ns) address inputs data inputs / outputs row address strobe input column address strobe input write control input power supply (+3.3v) ground (0v) output enable input
edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis row address address column input/output refresh remark hyper page mode identical cas before ras refresh ras-only refresh operation function in addition to normal read, write, and read-modify-write operations the m5m4v4405cj,tp provide, a number of other functions, e.g., hyper page mode, ras-only refresh, and delayed-write. the input conditions for each are shown in table 1. ras cas oe inputs w input output table 1 input conditions for each mode read write (early write) write (delayed write) read-modify-write stand-by hidden refresh self refresh * act act act act act act act nac act act act act nac act act dnc nac act act act dnc dnc nac dnc act dnc nac act dnc act dnc dnc apd apd apd apd apd dnc dnc dnc apd apd ap d apd dnc dnc dnc dnc opn apd apd apd dnc opn dnc dnc vld opn ivd vld opn vld opn opn yes yes yes yes yes yes yes no act act nac dnc dnc dnc dnc opn yes note : act : active, nac : nonactive, dnc : don' t care, vld : valid, ivd : invalid, apd : applied, opn : open sense refresh amplifer & i /o control row & column address buffer block diagram 2 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 address inputs v cc (3.3v) v ss (0v) oe dq 1 dq 2 dq 3 dq 4 column address strobe input row address strobe input write control input cas ras w a 0 ~ a 9 a 0 ~ a 9 clock generator circuit column decoder row decoder memory cell (4,194,304 bits) (4) data in buffers (4) data out buffers data inputs / outputs output enable input
edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis average supply current from v cc refreshing absolute maximum ratings ratings 3 symbol v cc v i v o i o p d t opr t stg parameter unit v v v ma mw -0.5 ~ 4.6 -0.5 ~ 4.6 50 1000 0 ~ 70 -65 ~ 150 ta=25 recommended operating conditions (ta=0~70?c, unless otherwise noted) (note 1) unit limits min nom max v v v v 3.6 0 0.8 3.3 0 3.0 0 2.0 parameter v cc symbol v ss v ih v il v cc +0.3 -0.3 electrical characteristics (ta=0~70?c, v cc =3.3v?0.3v, vs s= 0v, unless otherwise noted) (note 2) v oh v ol i oz i i high-level output voltage low-level output voltage off-state output current input current i oh =-2ma i ol =2ma q floating, 0v v out v cc 0v v in v cc +0.3v, other inputs pins=0v v v ? ? vcc 0.4 5 5 2.4 0 -5 -5 ras=cas 3 v cc -0.2v output open 70 note 2: current flowing into an ic is positive, out is negative. 3: i cc1 (av) , i cc3 (av) , i cc4 (av) and i cc6 (av) are dependent on cycle rate. maximum current is measured at the fastest cycle rate. 4: i cc1 (av) and i cc4 (av) are dependent on output loading. specified values are obtained with the output open. 5: column addres can be changed once or less while ras=v il and cas=v ih . c c c note 1 : all voltage values are with respect to v ss. symbol parameter test conditions unit limits min typ max dq 1 ~dq 4 0.8 -0.3 i cc8(av) * i cc9(av) * (note 6) average supply current from v cc extended-refresh cycle average supply current from v cc self-refresh cycle (note 6) ras cycling cas 0.2v or cas before ras refresh cycling ras 0.2v or 3 v cc -0.2v cas 0.2v or 3 v cc -0.2v w 0.2v (except for ras falling edge) or 3 v cc -0.2v oe 0.2v or 3 v cc -0.2v a 0 ~a 9 0.2v or 3 v cc -0.2v dq=open t rc =125?, t ras =t ras min ~1? ras=cas 0.2v output open ? 100 ? 100 m5m4v4405c-6,-6s m5m4v4405c-7,-7s i cc1 (av) i cc2 (av) average supply current from v cc operating (note 3,4,5) supply current from vc c , stand-by ras, cas cycling t rc =t wc =min. output open ras=cas =v ih , output open ma ma 80 2 0.5 (note 6) i cc3 (av) i cc4(av) i cc6(av) (note 3,5) (note 3,4,5) (note 3) average supply current from v cc hyper-page-mode average supply current from v cc, cas before ras refresh mode ras cycling, cas= v ih t rc =min. output open ras=v il , cas cycling t pc =min. output open cas before ras refresh cycling t rc =min. output open ma ma ma 80 70 80 70 70 60 m5m4v4405c-6,-6s m5m4v4405c-7,-7s m5m4v4405c-6,-6s m5m4v4405c-7,-7s m5m4v4405c-6,-6s m5m4v4405c-7,-7s 0.05 * conditions supply voltage supply voltage high-level input voltage, all inputs low-level input voltage others supply voltage input voltage output voltage output current power dissipation operating temperature storage temperature with respect to v ss -0.5 ~ 4.6 v m5m4v4405c m5m4v4405c(s) m5m4v4405c(s)
edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis test conditions 4 switching characteristics (ta=0~70?c, v cc =3.3v?.3v, vss = 0v, unless otherwise noted, see notes 6,14,15) ns ns ns ns 15 30 33 60 (note 7,8) (note 7,9) (note 7,10) (note 7,11) m5m4v4405c-6,-6s m5m4v4405c-7,-7s 20 35 38 70 parameter symbol limits unit min max min max t cac t rac t aa t cpa note 6: an initial pause of 200? is required after power-up followed by a minimum of eight initialization cycles (ras only refresh or cas before ras refresh cycles) ?d?@?@?@?@?@?@?@?@?@?@?@?@?@ ?@ note the ras may be cycled during the initial pause. and eight initialization cycles are required after prolonged periods (greater than t ref(max) ) of ras inactivity before proper device operation is achieved. 7: measured with a load circuit equivalent to 100pf, v oh =2.4v(i oh =-2ma) and v ol =0.4v(i ol =2ma). the reference levels for measuring of output signals are 2.0v(v oh ) and 0.8v(v ol ). 8: assumes that t rcd 3 t rcd(max) and t asc 3 t asc(max) and t cp 3 t cp(max) . 9: assumes that t rcd t rcd(max) and t rad t rad(max) . if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac will increase by amount that t rcd exceeds the value shown. 10: assumes that t rad 3 t rad(max) and t asc t asc(max) . 11: assumes that t cp t cp(max) and t asc 3 t asc(max) . 12: t oez (max) , t wez(max) , t off(max) and t rez(max) defines the time at which the output achieves the high impedance state( i out | ?0? |) and is not reference to v oh(min) or v ol(max) . 13: output is disabled after both ras and cas go to high. capacitance limits min max unit typ pf pf pf c i (a) c i (clk) c i / o symbol parameter 5 7 7 v i =v ss f=1mhz v i =25mvrms (ta=0~70?c, v cc =3.3v?.3v, vss = 0v, unless otherwise noted) t oea t clz t oez t off t wez t rez t ohc (note 12) (note 12,13) (note 7) ns 15 20 5 15 ns ns 15 ns 5 20 20 ns ns (note 12) (note 12,13) 15 15 20 20 5 ns 5 5 ns 5 t ohr ?@ (note 7) input capacitance, address inputs input capacitance, clock inputs input/output capacitance, data ports access time from cas access time from ras column address access time access time from cas precharge access time from oe output disable time after oe high output disable time after we low output disable time after cas high output disable time after ras high output low impedance time from cas low output hold time from cas output hold time from ras (note 13)
edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis parameter symbol limits unit min max min max parameter symbol limits unit min max min max timing requirements note 14: the timing requirements are assumed t t =2ns. ?@ 15: v ih(min) and v il(max) are reference levels for measuring timing of input signals. ?@ 16: t rcd(max) is specified as a reference point only. if t rcd is less than t rcd(max ), access time is t rac . if t rcd is greater than t rcd(max ), access time is controlled exclusively by t cac or t aa. ?@ 17: t rad(max) is specified as a reference point only. if t rad 3 t rad(max) and t asc t asc(max) , access time is controlled exclusively by t aa . ?@ 18: t asc(max) is specified as a reference point only. if t rcd 3 t rcd(max) and t asc 3 t asc(max) , access time is controlled exclusively by t cac . ?@ 19: either t dzc or t dzo must be satisfied. ?@ 20: either t rdd or t cdd or t odd must be satisfied. ?@ 21: t t is measured between v ih(min) and v il(max). (note 21) (note 16) (note 17) (note 18) 16.4 45 30 0 40 13 50 20 5 10 15 10 10 0 0 1 (note 19) (note 20) (note 19) (note 20) 0 0 15 15 ms ms ns ns ns ns ns ns ns ns 16.4 50 35 0 50 13 50 20 5 13 15 10 10 0 0 1 0 0 20 20 ns ns ns ns ns ns t ref t rp t rcd t crp t rpc t cpn t rad t asr t asc t rah t cah t dzc t dzo t cdd t odd t t m5m4v4405c-6,-6s m5m4v4405c-7,-7s read and refresh cycles note 22: either t rch or t rrh must be satisfied for a read cycle. (note 22) (note 22) 10000 10000 0 0 110 60 10 48 15 0 30 15 ns ns ns ns ns ns ns ns ns ns ns 10000 10000 0 0 130 70 13 55 20 0 35 20 15 20 t rc t ras t cas t csh t rsh t rcs t rch t rrh t ral t och t orh m5m4v4405c-6,-6s m5m4v4405c-7,-7s (for read, write, read-modify-write, refresh, and hyper-page mode cycles) 5 t ref 128 128 ns ns t cal 18 23 ns (note 20) 15 20 t rdd refresh cycle time ras high pulse width delay time, ras low to cas low delay time, cas high to ras low delay time, ras high to cas low cas high pulse width column address delay time from ras low row address setup time before ras low column address setup time before cas low row address hold time after ras low column address hold time after cas low transition time delay time, data to cas low delay time, data to oe low delay time, oe high to data delay time, ras high to data refresh cycle time * delay time, cas high to data read cycle time ras low pulse width cas low pulse width cas hold time after ras low read setup time before cas low read hold time after cas high ras hold time after cas low read hold time after ras high column address to ras hold time ras hold time after oe low column address to cas hold time cas hold time after oe low (ta=0~70?c, v cc = 3.3v?.3v, v ss =0v, unless otherwise noted, see notes 14,15)
edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis parameter symbol limits unit min max min max parameter symbol limits unit min max min max 6 write cycle (early write and delayed write) (note 24) 10000 10000 10 0 110 60 10 48 10 10 10 10 0 10 ns ns ns ns ns ns ns ns ns ns ns 10000 10000 13 0 130 70 13 55 13 13 13 13 0 13 ns t wc t ras t cas t csh t rsh t wcs t wch t cwl t rwl t wp t ds t dh m5m4v4405c-6,-6s m5m4v4405c-7,-7s read-write and read-modify-write cycles (note 23) (note 24) (note 24) (note 24) t rwc t ras t cas t csh t rsh t rcs t cwd t rwd t awd ns ns ns ns ns ns ns ns ns m5m4v4405c-6,-6s m5m4v4405c-7,-7s note 23: t rwc is specified as t rwc(min ) = t rac(max) + t odd(min) + t rwl(min) + t rp(min) +4 t t . ?@ 24: t wcs , t cwd , t rwd , t awd , and t cpwd are specified as reference points only. if t wcs 3 t wcs(min) the cycle is an early write cycle and the dq pins will remain high impedance throughout the entire cycle. if t cwd 3 t cwd(min) , t rwd 3 t rwd(min) , t awd 3 t awd(min) and t cpwd 3 t cpwd (min) (for fast page mode cycle only), the cycle is a read-modify-write cycle and the dq will contain the data read from the selected address. if neither of the above condition (delayed write) of the dq (at access time and until cas or oe goes back to v ih ) is indeterminate. 44 44 0 32 77 47 10000 10000 133 89 89 57 57 0 42 92 57 10000 10000 161 107 107 t oeh ns 15 20 write cycle time ras low pulse width cas low pulse width cas hold time after ras low write setup time before cas low write hold time after cas low ras hold time after cas low cas hold time after w low ras hold time after w low data setup time before cas low or w low data hold time after cas low or w low write pulse width read write/read modify write cycle time ras low pulse width cas low pulse width cas hold time after ras low ras hold time after cas low read setup time before0 cas low delay time, cas low to w low delay time, ras low to w low delay time, address to w low oe hold time after w low
edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis note 29: eight or more cas before ras cycles instead of eight ras cycles are necessary for proper operation of cas before ras refresh mode. parameter symbol limits unit min max min max parameter symbol limits unit min max min max parameter symbol limits unit min max min max t rps t chs t rass t rsr t rhr m5m4v4405c-6,-6s m5m4v4405c-7,-7s ns ns ns ns ns ns all previously specified timing requirements and switching characteristics are applicable to their respective hyper page mode cycle. t hpc(min) is specified in the case of read-only and early write-only in hyper page mode. t ras(min) is specified as two cycles of cas input are performed. t cp(max) ) is specified as a reference point only. 7 hyper page mode cycle (read, early write, read-write, read-modify-write cycle, read write mix cycle, hi-z control by cas before ras refresh cycle (note 29) 17 5 10 10 10 22 5 10 15 15 m5m4v4405c-6,-6s m5m4v4405c-7,-7s ns ns ns ns ns t csr t chr t cas t rsr t rhp self refresh cycle * (note 30) 10 100 -50 10 110 15 100 -50 10 130 m5m4v4405c-6,-6s m5m4v4405c-7,-7s ns ns ns ns ns ns ns ns ns ns ns ns ns ns 33 25 77 10 50 100000 16 66 7 7 7 38 30 92 13 60 100000 16 79 7 7 7 5 5 32 42 47 57 50 60 15 20 30 35 33 38 t hpc t hprwc t doh t ras t cp t cprh t cpwd t chol t oepe t wpe t hcwd t hawd t hpwd t hcod t haod t hpod (note 27) (note 28) (note 24) (note 26) note 25: 26: 27: 28: hyper page mode read/write cycle time ras low pulse width for read or write cycle cas high pulse width ras hold time after cas precharge delay time, cas precharge to w low hyper page mode read write / read modify write cycle time hold time to maintain the data hi-z until cas access oe pulse width (hi-z control) w pulse width (hi-z control) output hold time from cas low delay time, cas low to w low after read delay time, address to w low after read delay time, cas precharge to w low after read delay time, cas low to oe high after read delay time, address to oe high after read delay time, cas precharge to oe high after read cas setup time before ras low cas hold time after ras low read setup time before ras low read hold time after ras low cas low pulse width cbr self refresh ras low pulse width cbr self refresh ras high precharge time cbr self refresh cas hold time read setup time before ras low read hold time after ras low ? oe or w) (note 25)
edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis parameter symbol limits unit min max min max parameter symbol limits unit min max min max parameter symbol limits unit min max min max ras cycling, cas= v ih t rc =min. output open average supply current from v cc operating average supply current from v cc refreshing average supply current from v cc hyper-page-mode average supply current from v cc cas before ras refresh mode symbol parameter limits min max unit typ test conditions test mode specification (note 31) electrical characteristics (ta=0~70?c, v cc =3.3v?.3v, v ss =0v, unless otherwise noted) (note 2) m5m4v4405c-6,-6s m5m4v4405c-7,-7s i cc1 (av) (note 3,4,5) ma 85 i cc3 (av) i cc4(av) i cc6(av) (note 3,5) (note 3,4,5) (note 3) ma ma ma 85 75 85 75 75 65 m5m4v4405c-6,-6s m5m4v4405c-7,-7s m5m4v4405c-6,-6s m5m4v4405c-7,-7s m5m4v4405c-6,-6s m5m4v4405c-7,-7s 75 note 31: all previously specified electrical characteristics, switing characteristics, and timing requirements are applicable to that of test mode. switching characteristics (ta=0~70?c, v cc =3.3v?.3v, v ss =0v, unless otherwise noted, see notes 6,14,15) t cac t rac t aa t cpa t oea m5m4v4405c-6,-6s m5m4v4405c-7,-7s ns ns ns ns ns (note 7,8) (note 7,9) (note 7,10) (note 7,11) (note 7) 35 38 65 20 40 43 75 25 20 25 20 115 15 53 35 10000 65 25 135 18 60 40 10000 75 m5m4v4405c-6,-6s m5m4v4405c-7,-7s ns ns ns ns ns ns timing requirements (ta=0~70?c, v cc =3.3v?.3v, v ss =0v, unless otherwise noted, see notes 14,15) read and refresh cycles t ras t cas t csh t rsh t ral t rc t och t orh ns ns 10000 10000 20 20 25 25 49 138 49 94 37 10000 94 62 166 62 112 47 10000 112 m5m4v4405c-6,-6s m5m4v4405c-7,-7s ns ns ns ns ns ns read-write and read-modify-write cycles ns ns 10000 10000 82 52 97 62 (note 23) (note 24) (note 24) (note 24) t rwc t ras t cas t csh t rsh t cwd t rwd t awd t cal 23 28 ns 8 ras, cas cycling t rc =t wc =min. output open ras=v il , cas cycling t pc =min. output open cas before ras refresh cycling t rc =min. output open access time from cas access time from ras column address access time access time from cas precharge access time from oe read cycle time ras low pulse width cas low pulse width cas hold time after ras low ras hold time after cas low column address to ras hold time ras hold time after oe low column address to cas hold time cas hold time after oe low read write/read modify write cycle time ras low pulse width cas low pulse width cas hold time after ras low ras hold time after cas low delay time, cas low to w low delay time, ras low to w low delay time, address to w low
edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis parameter symbol limits unit min max min max 9 t whr t wsr test mode set cycle 10 10 10 15 m5m4v4405c-6,-6s m5m4v4405c-7,-7s ns ns hyper page mode cycle (read, early write, read-write, read-modify-write cycle, read write mix cycle, hi-z control by m5m4v4405c-6,-6s m5m4v4405c-7,-7s ns ns ns ns ns (note 26) (note 27) t hpc t hprwc t ras t cprh t cpwd ns ns ns ns ns ns (note 24) t hcwd t hawd t hpwd t hcod t haod t hpod 38 30 82 55 100000 71 43 35 97 65 100000 84 37 47 52 62 55 65 20 25 35 40 38 43 parameter symbol limits unit min max min max hyper page mode read/write cycle time ras low pulse width for read or write cycle ras hold time after cas precharge delay time, cas precharge to w low hyper page mode read write / read modify write cycle time delay time, cas low to w low after read delay time, address to w low after read delay time, cas precharge to w low after read delay time, cas low to oe high after read delay time, address to oe high after read delay time, cas precharge to oe high after read write setup time before ras low write hold time after ras low oe or w) (note 25)
edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis hi-z hi-z hi-z indicates the don't care input. v ih(min) v in v ih(max) or v il(min) v in v il(max) indicates the invalid output. timing diagrams (note 32) read cycle note 32 dq 1 ~dq 4 (inputs) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t csh t asc t cah t rcs t ras t rc t rsh t cas t ral t cac t aa t clz t rac t rch t rrh t asr t crp t rp row row address ras w dq 1 ~dq 4 (outputs) v ih v il oe address column address t dzc t oez t odd t oea t och t dzo t orh a 0 ~a 9 t rez t off t cal t ohr t ohc cas t cdd t wez data valid
edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis hi-z early write cycle dq 1 ~dq 4 (inputs) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rcd t csh t asc t cah t wcs t ras t wc t rsh t cas t wch t asr t crp t rp row column row address data valid ras w dq 1 ~dq 4 (outputs) v ih v il oe address address t ds t dh a 0 ~a 9 cas
edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis hi-z hi-z hi-z delayed write cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rcd t csh t asc t cah t rcs t ras t wc t rsh t cas t asr t crp t rp row column row address data valid address address t clz t wch t cwl t rwl t dh t ds t wp t dzc v ih v il t oez t dzo t odd t oeh dq 1 ~dq 4 (inputs) ras w dq 1 ~dq 4 (outputs) oe a 0 ~a 9 cas
edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis hi-z hi-z hi-z read-write, read-modify-write cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rcd t csh t asc t cah t rcs t ras t rwc t rsh t cas t asr t crp t rp row column row address data valid address address t clz t cwl t rwl t dh t ds t wp t dzc v ih v il t oez t dzo t odd t oeh t awd t cwd t rwd data valid t aa t cac t rac t oea t rad dq 1 ~dq 4 (inputs) ras w dq 1 ~dq 4 (outputs) oe a 0 ~a 9 cas
edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis hyper page mode read cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t rac t asr hi-z address column-1 row address t rp t cas row t asc t rcs hi-z t dzc v ih v il t dzo t oea t och data valid-1 t csh t hpc t cas t cp t cas t rsh column-2 column-3 t cah t asc t cah t asc t cprh t ral t rch t rrh t cdd t cpa t oez t odd t rez t off t clz t doh t rdd t cac t aa data valid-2 t cpa t doh t cac data valid-3 t aa t cal t cal t cal t ohc t ohr dq 1 ~dq 4 (inputs) ras w dq 1 ~dq 4 (outputs) oe a 0 ~a 9 cas t wez
edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis hi-z data valid-1 data valid-2 data valid-3 address row address row hyper page mode early write cycle t crp t asr t rah t rcd t cah t ras t cp t asr t rp t cas t asc t wcs t csh t hpc t cas t cp t cas t rsh t cah t cah t asc t asc t wch t wcs t wch t wcs t wch t ds t dh t ds t dh t ds t dh t cal t cal t crp a 0 ~a 9 dq 1 ~dq 4 (inputs) ras cas w dq 1 ~dq 4 (outputs) oe v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il column-1 column-2 column-3
edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis data valid-2 data valid-1 hi-z hi-z hi-z hi-z hi-z data valid-2 address row address row hyper page mode read-write, read-modify-write cycle t crp t asr t rah t rcd t cah t ras t cp t asr t rp t cas t asc t csh t hprwc t cas t rwl t cah t asc t rcs t rwd t dzc t ds t cwl t wp t rcs t wp t cwl t dh t ds t dzc t cpwd t dh t clz t dzo t oez t odd t oez t oeh t rad t cwd t awd t awd t cwd t aa t cac t aa t cac t clz t rac t oea t dzo t cpa t oea t odd t crp a 0 ~a 9 dq 1 ~dq 4 (inputs) ras cas w dq 1 ~dq 4 (outputs) oe v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il column-1 column-2 data valid-1
edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis hi-z address row t wch t dh hyper page mode mix cycle (1) t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t rac t rp t cas t asc t rcs t dzc t dzo t oea t och t csh t hpc t cas t cp t cas t cah t asc t cah t asc t hprwc t cpwd t wp t wcs t ds t clz t cpa t aa t cal t cal t cwd t oez t odd t wez t oeh t oez t clz t oea t asr t crp t cac t odd t dh t ds t rwl t cwl t dzo t dzc t awd a 0 ~a 9 dq 1 ~dq 4 (inputs) ras cas w dq 1 ~dq 4 (outputs) oe v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il column-1 row address column-2 column-3 data valid-2 data valid-3 data valid-3 data valid-1
edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis data valid-2 hi-z hi-z data valid-1 data valid-3 hi-z t cah t asc t aa t cac t oez t ds t odd t dh t dzc t cah t asc t cah t asc t cpa t aa t wch t cac t oea t clz t cpa t cal t cp t cas t rch t wcs t wez t cal hyper page mode mix cycle (2) t cas t hcod t haod t hpod t hcwd t hawd t hpwd a 0 ~a 9 dq 1 ~dq 4 (inputs) ras cas w dq 1 ~dq 4 (outputs) oe v ih v il v oh v ol v ih v il t dzc column-1 column-2 column-3 v ih v il v ih v il v ih v il v ih v il
edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis hi-z hi-z address row address row data valid-1 data valid-3 hi-z data valid-1 t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t rac t asr t rp t cas t asc t rcs t dzc t dzo t oea t csh t hpc t cas t cp t cas t rsh t cah t asc t cah t asc t cprh t ral t rch t rrh t cdd t cpa t oez t odd t rez t off t clz t doh t rdd t cac t aa t cpa t oez t cac t aa hyper page mode read cycle ( hi-z control by oe ) t clz t oepe t oepe t oez t oea t ohr t ohc t crp t wez a 0 ~a 9 dq 1 ~dq 4 (inputs) ras cas w dq 1 ~dq 4 (outputs) oe v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il t chol t och data valid-2 column-1 column-2 column-3
edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis hi-z address row address row hi-z data valid-3 hi-z t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t rac t asr t rp t cas t asc t rcs t dzc t dzo t oea t och t csh t hpc t cas t cp t cas t rsh t cah t asc t cah t asc t cprh t ral t rch t cdd t cpa t oez t odd t rez t off t clz t doh t rdd t cac t aa t cpa t wez t cac t aa hyper page mode read cycle ( hi-z control by w ) t wpe t rch t rcs t clz t ohr t ohc t rrh t crp t wez a 0 ~a 9 dq 1 ~dq 4 (inputs) ras cas w dq 1 ~dq 4 (outputs) oe v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il column-1 column-2 column-3 data valid-1 data valid-2
edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis row address hi-z row address t asr t rah t asr t crp t rpc a 0 ~a 9 dq 1 ~dq 4 (inputs) ras cas w dq 1 ~dq 4 (outputs) oe v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il ras-only refresh cycle t crp t ras t rc t rp
edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis hi-z row column address address a 0 ~a 9 dq 1 ~dq 4 (inputs) ras cas w dq 1 ~dq 4 (outputs) oe v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il cas before ras refresh cycle, extended refresh cycle* t rpc t ras t rc t asr t crp t rpc t rp t rc t ras t csr t chr t csr t rpc t cpn t rsr t rhr t rsr t rhr t rcs t off t oez t rp t chr t rrh t rch t rez t ohr t ohc
edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis hi-z hi-z hi-z note 33: early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. timing requirements and output state are the same as that of each cycle shown above. hidden refresh cycle (read) (note 33) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t cah t rcs t ras t rc t chr t cac t aa t clz t rac t rrh t asr t rp address column data valid t ras t rc t rp t rsh row t asc address t ral t dzc v ih v il t dzo t oea t orh t odd t oez t rez t cdd t rch t rdd t ohr t ohc t off dq 1 ~dq 4 (inputs) ras w dq 1 ~dq 4 (outputs) oe a 0 ~a 9 cas address row
edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis row address hi-z a 0 ~a 9 dq 1 ~dq 4 (inputs) ras cas w dq 1 ~dq 4 (outputs) oe v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il self refresh cycle* (note 30) t chs t rpc t rps t asr t crp t rass t csr t rch t rcs t off t oez t rp t rpc hi-z t cdd t odd t rsr t rhr t rrh t rdd t rez t ohr t ohc t cpn
edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis test mode set cycle (note 34) the cycle is also avaiilable for initialization cycle, but in this case device enters test mode. the test mode function is initiated with a w and cas before ras cycle(wcbr cycle) as specified above timing diagram. the test mode function is terminated by either a cas before ras(cbr) refresh or a ras only refresh cycle. during the test mode, the device is internally organized as 4-bits wide (256 kilobytes deep) for each dq (input / output) port. no addressing of a 0 , a 1 (column only) is required. during a write cycle, data on the each dq (input) pin is written in parallel into all 4-bits for each dq port and can be written independently for each dq port. during a read cycle, the each dq (output) pin indicates independently a high state if all 4-bits are equal, and a low state if any bits differ. during the test mode operation, a wcbr cycle is used to perform refresh. note 34 : cas w dq 1 ~dq 4 (inputs) ras v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t ras t rc t asr t crp t rpc t rp column address dq 1 ~dq 4 (outputs) row address t rpc t csr t chr t cpn t rch t rcs t off hi-z oe v ih v il t oez t rp a 0 ~a 9 t wsr t whr
edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis refresh cycle read/write cycles read/write cycles refresh cycle refresh cycle note 30 : self refresh sequence two refreshing methods should be used properly depending on the low pulse width(t rass ) of ras signal during self refresh period. 1. distributed refresh during read / write operation (a) timing diagram table 2 read / write cycle cbr distributed refresh ras only distributed refresh read / write self refresh self refresh read / write t nsd 16? t snd 16? t nsd 125? t snd 125? switching from read/write operation to self refresh operation. the time interval from the falling edge of ras signal in the last cbr refresh cycle during read/write operation period to the falling edge of ras signal at the start of self refresh operation should be set within t nsd (shown in table 2). definition of cbr distributed refresh (including extended refresh) note: hidden refresh may be used instead of cbr refresh. ras/cas refresh may be used instead of ras only refresh. 1.1 cbr distributed refresh the cbr distributed refresh performs more than 1024 constant period(125? max.) cbr cycles within 128 ms. all combinations of nine row address signals (a 0 ~a 9 ) are selected during 1024 constant period(16? max.) ras only refresh cycles within 16.4 ms. definition of ras only distributed refresh read / write cycle self refresh cycle read / write cycle t nsd t rass 3 100? t snd last refresh cycle first refresh cycle ras (b) definition of distributed refresh t ref t ref /1024 ras t ref /1024 switching from self refresh operation to read/write operation. the time interval from the rising edge of ras signal at the end of self refresh operation to the falling edge of ras signal in the first cbr refresh cycle during read/write operation period should be set within t snd (shown in table 2). switching from read/write operation to self refresh operation. the time interval t nsd from the falling edge of ras signal in the last ras only refresh cycle during read/write operation period to the falling edge of ras signal at the start of self refresh operation should be set within 16?. switching from self refresh operation to read/write operation. the time interval t snd from the rising edge of ras signal at the end of self refresh operation to the falling edge of ras signal in the first cbr refresh cycle during read/write operation period should be set within 16?. 1.2 ras only distributed refresh
edo (hyper page mode) 4194304-bit(1048576-word by 4-bit) dynamic ram m5m4v4405cj,tp-6,-7,-6s,-7s mitsubishi lsis read/write cycles refresh cycles 1024cycles last refresh cycles first refresh cycles refresh cycles 1024 cycles refresh cycles 1024 cycles read / write self refresh read / write 2. burst refresh during read/write operation (a) timing diagram table 3 read / write cycle cbr burst refresh ras only burst refresh read / write self refresh definition of cbr burst refresh (b) definition of burst refresh the cbr burst refresh performs more than 1024 continuous cbr cycles within 16.4 ms. all combination of nine row address signals (a 0 ~a 9 ) are selected during 1024 continuous ras only refresh cycles within 16.4 ms. definition of ras only burst refresh t nsb +t snb 16.4ms self refresh read / write t nsb 16.4ms t snb 16.4ms 2.1 cbr burst refresh 16.4ms ras t nsb t rass 3 100? t snb ras switching from read/write operation to self refresh operation. the time interval ns from the falling edge of ras signal in the first cbr refresh cycle during read/write operation period to the falling edge of ras signal at the start of self refresh operation should be set within 16.4 ms. switching from self refresh operation to read/write operation. the time interval snob from the rising edge of ras signal at the end of self refresh operation to the falling edge of ras signal in the last cbr refresh cycle during read/write operation period should be set within 16.4 ms. 2.2 ras only burst refresh switching from read/write operation to self refresh operation. the time interval from the falling edge of ras signal in the first ras only refresh cycle during read/write operation period to the falling edge of ras signal at the start of self refresh operation should be set within t nsb (shown in table 3). switching from self refresh operation to read/write operation. the time interval from the rising edge of ras signal at the end of self refresh operation to the falling edge of ras signal in the last ras only refresh cycle during read/write operation period should be set within t snb (shown in table 3).

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